BUFGMUX
BUFGMUX_BUFGMUX
- CLK_SEL_TYPE=[SYNC:1]
- DISABLE_ATTR=[LOW:1]
- S=[S_INV:0] [S:1]
BUFIO2FB_BUFIO2FB
- DIVIDE_BYPASS=[TRUE:2]
- INVERT_INPUTS=[FALSE:2]
BUFIO2_BUFIO2
- DIVIDE=[1:2]
- DIVIDE_BYPASS=[TRUE:2]
- I_INVERT=[FALSE:2]
DCM
- PSCLK=[PSCLK_INV:0] [PSCLK:2]
- PSEN=[PSEN_INV:0] [PSEN:2]
- PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
- RST=[RST:2] [RST_INV:0]
DCM_DCM
- CLKDV_DIVIDE=[2.0:2]
- CLKIN_DIVIDE_BY_2=[FALSE:2]
- CLKOUT_PHASE_SHIFT=[NONE:2]
- CLK_FEEDBACK=[1X:2]
- DESKEW_ADJUST=[5:2]
- DFS_FREQUENCY_MODE=[LOW:2]
- DLL_FREQUENCY_MODE=[LOW:2]
- DSS_MODE=[NONE:2]
- DUTY_CYCLE_CORRECTION=[TRUE:2]
- PSCLK=[PSCLK_INV:0] [PSCLK:2]
- PSEN=[PSEN_INV:0] [PSEN:2]
- PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
- RST=[RST:2] [RST_INV:0]
- STARTUP_WAIT=[FALSE:2]
- VERY_HIGH_FREQUENCY=[FALSE:2]
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FF_SR
- CK=[CK:838] [CK_INV:0]
- SRINIT=[SRINIT0:810] [SRINIT1:28]
- SYNC_ATTR=[ASYNC:746] [SYNC:92]
IOB_INBUF
IOB_OUTBUF
- DRIVEATTRBOX=[12:18]
- SLEW=[SLOW:18]
- SUSPEND=[3STATE:18]
LUT_OR_MEM5
- CLK=[CLK:47] [CLK_INV:0]
- LUT_OR_MEM=[LUT:2] [RAM:47]
- RAMMODE=[SPRAM32:4] [SRL16:43]
LUT_OR_MEM6
- CLK=[CLK:56] [CLK_INV:0]
- LUT_OR_MEM=[LUT:4] [RAM:56]
- RAMMODE=[SPRAM32:4] [SRL16:52]
OLOGIC2
- CLK0=[CLK0_INV:0] [CLK0:1]
- CLK1=[CLK1:0] [CLK1_INV:1]
OLOGIC2_OUTFF
- CK0=[CK0_INV:0] [CK0:1]
- CK1=[CK1_INV:1] [CK1:0]
- DDR_ALIGNMENT=[NONE:1]
- OUTFFTYPE=[DDR:1]
- SRINIT_OQ=[0:1]
- SRTYPE_OQ=[SYNC:1]
RAMB16BWER
- CLKA=[CLKA_INV:0] [CLKA:16]
- CLKB=[CLKB_INV:0] [CLKB:16]
- ENA=[ENA_INV:0] [ENA:16]
- ENB=[ENB_INV:0] [ENB:16]
- REGCEA=[REGCEA_INV:0] [REGCEA:16]
- REGCEB=[REGCEB_INV:0] [REGCEB:16]
- RSTA=[RSTA:16] [RSTA_INV:0]
- RSTB=[RSTB:16] [RSTB_INV:0]
- WEA0=[WEA0:16] [WEA0_INV:0]
- WEA1=[WEA1:16] [WEA1_INV:0]
- WEA2=[WEA2:16] [WEA2_INV:0]
- WEA3=[WEA3_INV:0] [WEA3:16]
- WEB0=[WEB0:16] [WEB0_INV:0]
- WEB1=[WEB1:16] [WEB1_INV:0]
- WEB2=[WEB2_INV:0] [WEB2:16]
- WEB3=[WEB3:16] [WEB3_INV:0]
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RAMB16BWER_RAMB16BWER
- CLKA=[CLKA_INV:0] [CLKA:16]
- CLKB=[CLKB_INV:0] [CLKB:16]
- DATA_WIDTH_A=[1:8] [4:2] [9:6]
- DATA_WIDTH_B=[1:8] [4:2] [9:6]
- DOA_REG=[0:16]
- DOB_REG=[0:1] [1:15]
- ENA=[ENA_INV:0] [ENA:16]
- ENB=[ENB_INV:0] [ENB:16]
- EN_RSTRAM_A=[FALSE:1] [TRUE:15]
- EN_RSTRAM_B=[TRUE:16]
- RAM_MODE=[TDP:16]
- REGCEA=[REGCEA_INV:0] [REGCEA:16]
- REGCEB=[REGCEB_INV:0] [REGCEB:16]
- RSTA=[RSTA:16] [RSTA_INV:0]
- RSTB=[RSTB:16] [RSTB_INV:0]
- RSTTYPE=[SYNC:16]
- RST_PRIORITY_A=[CE:16]
- RST_PRIORITY_B=[CE:16]
- WEA0=[WEA0:16] [WEA0_INV:0]
- WEA1=[WEA1:16] [WEA1_INV:0]
- WEA2=[WEA2:16] [WEA2_INV:0]
- WEA3=[WEA3_INV:0] [WEA3:16]
- WEB0=[WEB0:16] [WEB0_INV:0]
- WEB1=[WEB1:16] [WEB1_INV:0]
- WEB2=[WEB2_INV:0] [WEB2:16]
- WEB3=[WEB3:16] [WEB3_INV:0]
- WRITE_MODE_A=[READ_FIRST:16]
- WRITE_MODE_B=[WRITE_FIRST:15] [READ_FIRST:1]
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REG_SR
- CK=[CK:3401] [CK_INV:0]
- LATCH_OR_FF=[FF:3399] [LATCH:2]
- SRINIT=[SRINIT0:3237] [SRINIT1:164]
- SYNC_ATTR=[ASYNC:2839] [SYNC:562]
SLICEL
- CLK=[CLK:324] [CLK_INV:0]
SLICEM
SLICEX
- CLK=[CLK:1064] [CLK_INV:0]
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