Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 
 
Software Version and Target Device
Product Version: ISE:11.5 (WebPack) Target Family: spartan6
OS Platform: NT Target Device: xc6slx16
Project ID (random number) 14d4066ba0c24e6cb7ba5e788a5cb51a.38795e2ae3014f8ba3afd65f709a0410.7 Target Package: csg324
Registration ID e Target Speed: -3
Date Generated 火 12 14 13:33:27 2010
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=149
  • Flip-Flops=149
 Counters=4
  • 11-bit down counter=2
  • 24-bit up counter=1
  • 7-bit down counter=1
 Adders/Subtractors=1
  • 9-bit subtractor=1
 Multiplexers=2
  • 8-bit 16-to-1 multiplexer=1
  • 9-bit 2-to-1 multiplexer=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=38
  • AGG_IO=38
  • AGG_LOCED_IO=38
  • AGG_SLICE=1555
  • NUM_BONDED_IOB=38
  • NUM_BSFULL=3186
  • NUM_BSLUTONLY=920
  • NUM_BSREGONLY=215
  • NUM_BSUSED=4321
  • NUM_BUFG=5
  • NUM_BUFGMUX=1
  • NUM_BUFIO2=2
  • NUM_BUFIO2FB=2
  • NUM_DCM=2
  • NUM_IOB_FF=1
  • NUM_LOCED_IOB=38
  • NUM_LOGIC_O5ANDO6=576
  • NUM_LOGIC_O5ONLY=252
  • NUM_LOGIC_O6ONLY=2611
  • NUM_LUT_RT_DRIVES_CARRY4=20
  • NUM_LUT_RT_DRIVES_FLOP=589
  • NUM_LUT_RT_DRIVES_OTHERS=2
  • NUM_LUT_RT_EXO5=589
  • NUM_LUT_RT_EXO6=22
  • NUM_LUT_RT_O5=118
  • NUM_LUT_RT_O6=250
  • NUM_OLOGIC2=1
  • NUM_RAMB16BWER=16
  • NUM_SLICEL=410
  • NUM_SLICEM=17
  • NUM_SLICEX=1128
  • NUM_SLICE_CARRY4=297
  • NUM_SLICE_CONTROLSET=192
  • NUM_SLICE_CYINIT=5151
  • NUM_SLICE_F7MUX=115
  • NUM_SLICE_FF=4237
  • NUM_SLICE_LATCHTHRU=2
  • NUM_SLICE_UNUSEDCTRL=150
  • NUM_SPRAM_O5ANDO6=4
  • NUM_SRL_O5ANDO6=43
  • NUM_SRL_O6ONLY=9
  • NUM_UNUSABLE_FF_BELS=564
  • Xilinx Core fifo_generator_v5_3, Xilinx CORE Generator 11.4=1
 		NetStatistics
  • NumNets_Active=5470
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=74
  • NumNodesOfType_Active_BOUNCEIN=766
  • NumNodesOfType_Active_BUFGOUT=6
  • NumNodesOfType_Active_BUFHINP2OUT=20
  • NumNodesOfType_Active_BUFIOINP=4
  • NumNodesOfType_Active_CLKPIN=1405
  • NumNodesOfType_Active_CLKPINFEED=38
  • NumNodesOfType_Active_CNTRLPIN=1192
  • NumNodesOfType_Active_DOUBLE=7437
  • NumNodesOfType_Active_GENERIC=61
  • NumNodesOfType_Active_GLOBAL=275
  • NumNodesOfType_Active_INPUT=858
  • NumNodesOfType_Active_IOBIN2OUT=35
  • NumNodesOfType_Active_IOBOUTPUT=36
  • NumNodesOfType_Active_LUTINPUT=12416
  • NumNodesOfType_Active_OUTBOUND=5293
  • NumNodesOfType_Active_OUTPUT=5470
  • NumNodesOfType_Active_PADINPUT=19
  • NumNodesOfType_Active_PADOUTPUT=20
  • NumNodesOfType_Active_PINBOUNCE=3518
  • NumNodesOfType_Active_PINFEED=14983
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=4
  • NumNodesOfType_Active_QUAD=4134
  • NumNodesOfType_Active_REGINPUT=1417
  • NumNodesOfType_Active_SINGLE=9108
  • NumNodesOfType_Gnd_BOUNCEIN=150
  • NumNodesOfType_Gnd_CLKPIN=4
  • NumNodesOfType_Gnd_CNTRLPIN=5
  • NumNodesOfType_Gnd_DOUBLE=22
  • NumNodesOfType_Gnd_GENERIC=1
  • NumNodesOfType_Gnd_HGNDOUT=83
  • NumNodesOfType_Gnd_INPUT=185
  • NumNodesOfType_Gnd_IOBIN2OUT=1
  • NumNodesOfType_Gnd_IOBINPUT=1
  • NumNodesOfType_Gnd_IOBOUTPUT=1
  • NumNodesOfType_Gnd_LUTINPUT=194
  • NumNodesOfType_Gnd_OUTBOUND=43
  • NumNodesOfType_Gnd_OUTPUT=51
  • NumNodesOfType_Gnd_PADINPUT=1
  • NumNodesOfType_Gnd_PINBOUNCE=109
  • NumNodesOfType_Gnd_PINFEED=382
  • NumNodesOfType_Gnd_REGINPUT=38
  • NumNodesOfType_Gnd_SINGLE=42
  • NumNodesOfType_Vcc_CNTRLPIN=23
  • NumNodesOfType_Vcc_HVCCOUT=396
  • NumNodesOfType_Vcc_INPUT=45
  • NumNodesOfType_Vcc_IOBIN2OUT=1
  • NumNodesOfType_Vcc_KVCCOUT=37
  • NumNodesOfType_Vcc_LUTINPUT=1073
  • NumNodesOfType_Vcc_PINBOUNCE=21
  • NumNodesOfType_Vcc_PINFEED=1124
  • NumNodesOfType_Vcc_REGINPUT=3
 SiteStatistics
  • BUFG-BUFGMUX=5
  • IOB-IOBM=15
  • IOB-IOBS=23
  • SLICEL-SLICEM=210
  • SLICEX-SLICEL=224
  • SLICEX-SLICEM=197
 		SiteSummary
  • BUFG=5
  • BUFGMUX=1
  • BUFGMUX_BUFGMUX=1
  • BUFG_BUFG=5
  • BUFIO2=2
  • BUFIO2FB=2
  • BUFIO2FB_BUFIO2FB=2
  • BUFIO2_BUFIO2=2
  • CARRY4=297
  • DCM=2
  • DCM_DCM=2
  • FF_SR=838
  • HARD0=25
  • HARD1=29
  • IOB=38
  • IOB_IMUX=20
  • IOB_INBUF=20
  • IOB_OUTBUF=18
  • LUT5=1533
  • LUT6=3455
  • LUT_OR_MEM5=49
  • LUT_OR_MEM6=60
  • NULLMUX=1
  • OLOGIC2=1
  • OLOGIC2_OUTFF=1
  • PAD=38
  • RAMB16BWER=16
  • RAMB16BWER_RAMB16BWER=16
  • REG_SR=3401
  • SELMUX2_1=115
  • SLICEL=410
  • SLICEM=17
  • SLICEX=1128
 
Configuration Data
BUFGMUX
  • S=[S_INV:0] [S:1]
 BUFGMUX_BUFGMUX
  • CLK_SEL_TYPE=[SYNC:1]
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:0] [S:1]
 BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:2]
  • INVERT_INPUTS=[FALSE:2]
 BUFIO2_BUFIO2
  • DIVIDE=[1:2]
  • DIVIDE_BYPASS=[TRUE:2]
  • I_INVERT=[FALSE:2]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2.0:2]
  • CLKIN_DIVIDE_BY_2=[FALSE:2]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[5:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DSS_MODE=[NONE:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:2]
  • VERY_HIGH_FREQUENCY=[FALSE:2]
 FF_SR
  • CK=[CK:838] [CK_INV:0]
  • SRINIT=[SRINIT0:810] [SRINIT1:28]
  • SYNC_ATTR=[ASYNC:746] [SYNC:92]
 IOB_INBUF
  • DIFF_TERM=[FALSE:1]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:18]
  • SLEW=[SLOW:18]
  • SUSPEND=[3STATE:18]
 LUT_OR_MEM5
  • CLK=[CLK:47] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:2] [RAM:47]
  • RAMMODE=[SPRAM32:4] [SRL16:43]
 LUT_OR_MEM6
  • CLK=[CLK:56] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:4] [RAM:56]
  • RAMMODE=[SPRAM32:4] [SRL16:52]
 OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
  • CLK1=[CLK1:0] [CLK1_INV:1]
 OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:1]
  • CK1=[CK1_INV:1] [CK1:0]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[DDR:1]
  • SRINIT_OQ=[0:1]
  • SRTYPE_OQ=[SYNC:1]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • REGCEA=[REGCEA_INV:0] [REGCEA:16]
  • REGCEB=[REGCEB_INV:0] [REGCEB:16]
  • RSTA=[RSTA:16] [RSTA_INV:0]
  • RSTB=[RSTB:16] [RSTB_INV:0]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • DATA_WIDTH_A=[1:8] [4:2] [9:6]
  • DATA_WIDTH_B=[1:8] [4:2] [9:6]
  • DOA_REG=[0:16]
  • DOB_REG=[0:1] [1:15]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • EN_RSTRAM_A=[FALSE:1] [TRUE:15]
  • EN_RSTRAM_B=[TRUE:16]
  • RAM_MODE=[TDP:16]
  • REGCEA=[REGCEA_INV:0] [REGCEA:16]
  • REGCEB=[REGCEB_INV:0] [REGCEB:16]
  • RSTA=[RSTA:16] [RSTA_INV:0]
  • RSTB=[RSTB:16] [RSTB_INV:0]
  • RSTTYPE=[SYNC:16]
  • RST_PRIORITY_A=[CE:16]
  • RST_PRIORITY_B=[CE:16]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
  • WRITE_MODE_A=[READ_FIRST:16]
  • WRITE_MODE_B=[WRITE_FIRST:15] [READ_FIRST:1]
 REG_SR
  • CK=[CK:3401] [CK_INV:0]
  • LATCH_OR_FF=[FF:3399] [LATCH:2]
  • SRINIT=[SRINIT0:3237] [SRINIT1:164]
  • SYNC_ATTR=[ASYNC:2839] [SYNC:562]
 SLICEL
  • CLK=[CLK:324] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:17] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:1064] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=5
  • O=5
 BUFGMUX
  • I0=1
  • I1=1
  • O=1
  • S=1
 BUFGMUX_BUFGMUX
  • I0=1
  • I1=1
  • O=1
  • S=1
 BUFG_BUFG
  • I0=5
  • O=5
 BUFIO2
  • DIVCLK=2
  • I=2
 BUFIO2FB
  • I=2
  • O=2
 BUFIO2FB_BUFIO2FB
  • I=2
  • O=2
 BUFIO2_BUFIO2
  • DIVCLK=2
  • I=2
 CARRY4
  • CIN=222
  • CO1=7
  • CO2=6
  • CO3=225
  • CYINIT=75
  • DI0=284
  • DI1=282
  • DI2=259
  • DI3=221
  • O0=257
  • O1=246
  • O2=246
  • O3=231
  • S0=297
  • S1=286
  • S2=277
  • S3=255
 DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
 DCM_DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
 FF_SR
  • CE=446
  • CK=838
  • D=838
  • Q=838
  • SR=382
 HARD0
  • 0=25
 HARD1
  • 1=29
 IOB
  • DIFFI_IN=1
  • I=20
  • O=18
  • PAD=38
  • PADOUT=1
  • T=1
 IOB_IMUX
  • I=20
  • OUT=20
 IOB_INBUF
  • DIFFI_IN=1
  • OUT=20
  • PAD=20
 IOB_OUTBUF
  • IN=18
  • OUT=18
  • TRI=1
 LUT5
  • A1=62
  • A2=132
  • A3=177
  • A4=201
  • A5=684
  • O5=1533
 LUT6
  • A1=715
  • A2=1120
  • A3=1625
  • A4=2601
  • A5=3117
  • A6=3405
  • O6=3455
 LUT_OR_MEM5
  • A1=47
  • A2=48
  • A3=48
  • A4=49
  • A5=49
  • CLK=47
  • DI1=47
  • O5=49
  • WA1=4
  • WA2=4
  • WA3=4
  • WA4=4
  • WA5=4
  • WE=47
 LUT_OR_MEM6
  • A1=56
  • A2=58
  • A3=58
  • A4=59
  • A5=60
  • A6=60
  • CLK=56
  • DI2=56
  • O6=60
  • WA1=4
  • WA2=4
  • WA3=4
  • WA4=4
  • WA5=4
  • WA6=4
  • WE=56
 NULLMUX
  • 0=1
  • OUT=1
 OLOGIC2
  • CLK0=1
  • CLK1=1
  • D1=1
  • D2=1
  • OCE=1
  • OQ=1
  • SR=1
 OLOGIC2_OUTFF
  • CE=1
  • CK0=1
  • CK1=1
  • D1=1
  • D2=1
  • Q=1
  • SR=1
 PAD
  • PAD=38
 RAMB16BWER
  • ADDRA0=9
  • ADDRA1=9
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=11
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB0=9
  • ADDRB1=9
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=11
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIA0=16
  • DIA1=8
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=8
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=8
  • DIA30=1
  • DIA31=1
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=6
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOB0=16
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • DOB4=6
  • DOB5=6
  • DOB6=6
  • DOB7=6
  • DOPB0=2
  • ENA=16
  • ENB=16
  • REGCEA=16
  • REGCEB=16
  • RSTA=16
  • RSTB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
 RAMB16BWER_RAMB16BWER
  • ADDRA0=9
  • ADDRA1=9
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=11
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB0=9
  • ADDRB1=9
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=11
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIA0=16
  • DIA1=8
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=8
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=8
  • DIA30=1
  • DIA31=1
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=6
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOB0=16
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • DOB4=6
  • DOB5=6
  • DOB6=6
  • DOB7=6
  • DOPB0=2
  • ENA=16
  • ENB=16
  • REGCEA=16
  • REGCEB=16
  • RSTA=16
  • RSTB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
 REG_SR
  • CE=1560
  • CK=3401
  • D=3401
  • Q=3401
  • SR=1379
 SELMUX2_1
  • 0=115
  • 1=115
  • OUT=115
  • S0=115
 SLICEL
  • A=28
  • A1=29
  • A2=53
  • A3=120
  • A4=200
  • A5=286
  • A6=338
  • AMUX=73
  • AQ=254
  • AX=139
  • B=27
  • B1=22
  • B2=38
  • B3=101
  • B4=183
  • B5=268
  • B6=313
  • BMUX=64
  • BQ=223
  • BX=114
  • C1=90
  • C2=113
  • C3=181
  • C4=259
  • C5=328
  • C6=378
  • CE=150
  • CIN=221
  • CLK=324
  • CMUX=116
  • COUT=222
  • CQ=267
  • CX=213
  • D=2
  • D1=90
  • D2=117
  • D3=177
  • D4=244
  • D5=313
  • D6=359
  • DMUX=54
  • DQ=211
  • DX=98
  • SR=160
 SLICEM
  • A=2
  • A1=15
  • A2=17
  • A3=17
  • A4=17
  • A5=17
  • A6=17
  • AI=15
  • AMUX=13
  • AQ=15
  • AX=14
  • B=1
  • B1=13
  • B2=13
  • B3=13
  • B4=14
  • B5=14
  • B6=14
  • BI=13
  • BMUX=13
  • BQ=12
  • BX=12
  • C=1
  • C1=14
  • C2=14
  • C3=14
  • C4=14
  • C5=14
  • C6=14
  • CE=17
  • CI=14
  • CIN=1
  • CLK=17
  • CMUX=11
  • CQ=13
  • CX=11
  • D=1
  • D1=14
  • D2=14
  • D3=14
  • D4=14
  • D5=15
  • D6=15
  • DI=14
  • DMUX=11
  • DQ=14
  • DX=11
 SLICEX
  • A=134
  • A1=159
  • A2=294
  • A3=402
  • A4=632
  • A5=844
  • A6=721
  • AMUX=282
  • AQ=945
  • AX=335
  • B=173
  • B1=163
  • B2=212
  • B3=275
  • B4=444
  • B5=615
  • B6=492
  • BMUX=213
  • BQ=525
  • BX=204
  • C=45
  • C1=90
  • C2=175
  • C3=214
  • C4=358
  • C5=502
  • C6=391
  • CE=408
  • CLK=1064
  • CMUX=157
  • CQ=494
  • CX=146
  • D=147
  • D1=115
  • D2=155
  • D3=203
  • D4=354
  • D5=509
  • D6=413
  • DMUX=137
  • DQ=428
  • DX=161
  • SR=476
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc6slx16-csg324-3 -w -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
_impact 383 379 0 0 0 0 0
arwz 2 2 0 0 0 0 0
bitgen 241 241 0 0 0 0 0
edif2ngd 6 6 0 0 0 0 0
map 275 254 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngdbuild 326 326 0 0 0 0 0
par 254 244 9 0 0 0 0
trce 244 244 0 0 0 0 0
xst 391 388 0 0 0 0 0
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISim (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=Verilog
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=0
FILE_UCF=1 FILE_VERILOG=1
PROP_DevDevice=xc6slx16 PROP_DevFamily=Spartan6
PROP_FitterReportFormat=HTML PROP_Simulator=ISim (VHDL/Verilog)
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No Project duration(days)=126
 
Core Statistics
Core Type=clk_wiz_v1_4
clkin1_period=5.0 clkin2_period=5.0 diff_ext_feedback=false feedback_source=FDBK_AUTO
num_out_clk=1 primtype_sel=DCM_SP use_dyn_phase_shift=false use_dyn_reconfig=false
use_inclk_switchover=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false
Core Type=fifo_generator_v5_3
c_common_clock=1 c_data_count_width=11 c_din_width=8 c_dout_rst_val=0
c_dout_width=8 c_enable_rst_sync=1 c_error_injection_type=0 c_full_flags_rst_val=1
c_has_almost_empty=0 c_has_almost_full=0 c_has_data_count=1 c_has_int_clk=0
c_has_overflow=0 c_has_rd_data_count=0 c_has_rst=1 c_has_srst=0
c_has_underflow=0 c_has_valid=1 c_has_wr_ack=0 c_has_wr_data_count=0
c_implementation_type=0 c_memory_type=1 c_msgon_val=1 c_overflow_low=0
c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=2kx9 c_prog_empty_thresh_assert_val=2
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=2046 c_prog_full_thresh_negate_val=2045
c_prog_full_type=0 c_rd_data_count_width=11 c_rd_depth=2048 c_rd_freq=1
c_rd_pntr_width=11 c_underflow_low=0 c_use_dout_rst=1 c_use_ecc=0
c_use_embedded_reg=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=11 c_wr_depth=2048 c_wr_freq=1 c_wr_pntr_width=11
Core Type=clk_wiz_v1_4
clkin1_period=5.0 clkin2_period=5.0 diff_ext_feedback=false feedback_source=FDBK_AUTO
num_out_clk=1 primtype_sel=DCM_SP use_dyn_phase_shift=false use_dyn_reconfig=false
use_inclk_switchover=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false
 
Par Statistics
Total Non-vccgnd Signals=5431
Total Non-vccgnd Design Pins=17311
Total Non-vccgnd Conns=17311
Total Non-vccgnd Timing Constrained Conns=16757
Phase 1 CPU=11.0 sec
Phase 2 CPU=13.8 sec
Phase 3 CPU=30.6 sec
Phase 4 CPU=32.0 sec
Phase 5 CPU=45.5 sec
Phase 6 CPU=45.5 sec
Phase 7 CPU=45.5 sec
Phase 8 CPU=45.5 sec
Phase 9 CPU=45.5 sec
Phase 10 CPU=48.2 sec
AvgWirelenPerPin Fanout 1=2.0
AvgWirelenPerPin Fanout 2=2.5
AvgWirelenPerPin Fanout 3=3.0
AvgWirelenPerPin Fanout 4=4.3
AvgWirelenPerPin Fanout 10=2.4
AvgWirelenPerPin Fanout 50=3.8
AvgWirelenPerPin Fanout 100=9.6
AvgWirelenPerPin Fanout 500=5.7
AvgWirelenPerPin Fanout 5000=4.6
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
IRR Gamma=4.2312