ISE11 Project Status (12/14/2010 - 11:56:07)
Project File: ISE11.ise Implementation State: Programming File Generated
Module Name: XC6S_SP601_SiTCP
  • Errors:
No Errors
Target Device: xc6slx16-3csg324
  • Warnings:
77 Warnings
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,239 18,224 23%  
    Number used as Flip Flops 4,237      
    Number used as Latches 0      
    Number used as Latch-thrus 2      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,106 9,112 45%  
    Number used as logic 3,439 9,112 37%  
        Number using O6 output only 2,611      
        Number using O5 output only 252      
        Number using O5 and O6 576      
        Number used as ROM 0      
    Number used as Memory 56 2,176 2%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 4      
            Number using O6 output only 0      
            Number using O5 output only 0      
            Number using O5 and O6 4      
        Number used as Shift Register 52      
            Number using O6 output only 9      
            Number using O5 output only 0      
            Number using O5 and O6 43      
    Number used exclusively as route-thrus 611      
        Number with same-slice register load 589      
        Number with same-slice carry load 20      
        Number with other load 2      
Number of occupied Slices 1,555 2,278 68%  
Number of LUT Flip Flop pairs used 4,321      
    Number with an unused Flip Flop 920 4,321 21%  
    Number with an unused LUT 215 4,321 4%  
    Number of fully used LUT-FF pairs 3,186 4,321 73%  
    Number of unique control sets 192      
    Number of slice register sites lost
        to control set restrictions
564 18,224 3%  
Number of bonded IOBs 38 232 16%  
    Number of LOCed IOBs 38 38 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 16 32 50%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 2 32 6%  
    Number used as BUFIO2FBs 2      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 6 16 37%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 2 4 50%  
    Number used as DCMs 2      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 1 248 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Average Fanout of Non-Clock Nets 3.40      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent‰Î 12 14 13:28:53 2010067 Warnings18 Infos
Translation ReportCurrent‰Î 12 14 13:29:03 2010000
Map ReportCurrent‰Î 12 14 13:31:56 201005 Warnings9 Infos
Place and Route ReportCurrent‰Î 12 14 13:32:54 201004 Warnings2 Infos
Power Report     
Post-PAR Static Timing ReportCurrent‰Î 12 14 13:33:07 2010003 Infos
Bitgen ReportCurrent‰Î 12 14 13:33:27 201001 Warning2 Infos
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/14/2010 - 13:52:41
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